It is well known to construct a synchronous first-in first-out (FIFO) buffer including logic indicating when the FIFO is full or empty. In a typical synchronous FIFO full and empty status flags are updated by a single clock, either a read clock or a write clock. The logic to generate the full and empty flags typically consists of counters, adders, combinatorial logic to generate a so called internal full-1(empty+1)flag and a final output register. An alternate way to generate the internal full flag is by directly decoding the counter outputs using combinatorial logic. The register is typically a master-slave register. The register architecture may use both the look-ahead internal flag (full-1 or empty+1) and the non look-ahead internal flag (full or empty) or just the internal look-ahead flag. The register architectures which use both look-ahead and non look-ahead flags are simple, whereas the architectures which use only one internal flag have a complex resetting mechanism of the master-slave after the first read or the first write. Typically the full or empty flag is updated by the write or read clock.
The minimum delay between the clocks is defined as a tSKEW delay. The updating clock, either the write or read clock, is guaranteed to recognize the second clock, either the read or write clock, if it occurs at least tSKEW delay ahead of the updation clock. If the second (read) clock occurs within tSKEW time from the updation clock (write), the updation clock may or may not recognize the second clock.
In a counter/adder decode method there are two counters, one each for the read and write clocks. These two counters are reset to zero upon master reset and are incremented based only on their respective clocks. The outputs of these counters are fed into a subtractor that perform Wcount-Rcount, or the difference between the number of locations written and the number of locations read. This difference is then fed into combinatorial logic to determine if the FIFO is full or full-1 (empty or empty+1). The combinatorial logic output is used as the input to the D-register which is clocked by the appropriate external clock.
Another method, called the direct decode method, uses the counters just like the counter/adder method. Instead of having a subtractor on the outputs, combinatorial logic is used to decode when the FIFO is full. This is done by taking the exclusive-OR (XOR) of the Wcount and the Rcount. This combinatorial logic can be arrived at by generating the truth table for the full (empty) flag with respect to the Wcount and Rcount input variables. This direct decode method greatly reduces the amount of logic required to generate an internal full status flag and improves the tSKEW delay.
The output register architectures which make use of both the look-ahead and non look-ahead internal flags are simple. These architectures have a multiplexer that is used to select either the free running clock or the enable clock. This selection is done by the output of the slave register.
The other alternate register implementation is accomplished exclusively with the internal look-ahead flag. The register receives the clock as long as the external flag is not active. When the external flag goes active, indicating a boundary condition, the master and slave registers are frozen by special logic. After the first read (full) or write (empty) the next clock resets the master and slave registers and enables the register clock. The reset logic design is typically very involved and complex.
All the above architectures suffer from very high tSKEW delays (.about.8-10 Gate Delays). Additionally these architectures also suffer from metastabilty problems introduced by the register trying to sample the asynchronous internal flag which is updated by both the asynchronous read and write clocks. The present invention solves both of these issues by providing very high MTBF and very short, even Ons tSKEW. Additionally the present invention gives designers the flexibility to program the tSKEW to any desired value, including a Ons tSKEW. The synchronous FIFO's require a flag updation cycle at the empty and full boundaries. Typically the fall through read timing (read after the first write), which is the worst, defines the clocking frequency. Although the flexibility to program the tSKEW to Ons is idealistic, the tSKEW does need to be programmed based on the fall through timing, which typically results in higher tSKEW requirements.